Memory system and method for controlling nonvolatile memory

ABSTRACT

According to one embodiment, a memory system is configured to operate as one of semiconductor storage devices in a storage array. The memory system includes a nonvolatile memory and a controller. The controller executes a write operation of writing data, received from a host, to the nonvolatile memory. The controller receives, from the host or another semiconductor storage device in the storage array, a notification indicative of a value related to an amount of reduction in write performance of the another semiconductor device. The controller reduces performance of the write operation based on the value notified by the received notification.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2015-249554, filed Dec. 22, 2015, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to technology forcontrolling a nonvolatile memory.

BACKGROUND

Recently, memory systems comprising nonvolatile memories have becomewidespread.

As one of these memory systems, a NAND flash solid state drive (SSD) isknown.

Because of their low-power consumption and high-performance, SSDs areused as the main storage of various computers.

Further, an array technique utilizing a plurality of SSDs has also beendeveloped in order to obtain higher performance and larger capacity.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for illustrating a configuration example of aninformation processing system including a storage array, to which amemory system according to an embodiment is applied.

FIG. 2 is a block diagram for illustrating another configuration exampleof the information processing system including the storage array, towhich the memory system according to the embodiment is applied.

FIG. 3 is a view for illustrating a write operation example of thestorage array.

FIG. 4 is a view for illustrating a write operation of the storage arrayperformed when the write performance of a certain SSD in the storagearray is reduced.

FIG. 5 is a view for illustrating a garbage collection (GC) operationperformed by other SSDs in the storage array during a period in whichthe write performance of a certain SSD in the storage array is reduced.

FIG. 6 is a view for illustrating a write operation and a GC operationperformed by other SSDs in the storage array during a period in whichthe write performance of a certain SSD in the storage array is reduced.

FIG. 7 is a view for illustrating a throttling operation performed byother SSDs in the storage array during a period in which the writeperformance of a certain SSD in the storage array is reduced.

FIG. 8 is a block diagram for illustrating a configuration example of amemory system functioning as a sending-side SSD.

FIG. 9 is a view for illustrating an operation of successivelyallocating free blocks for writing of data from a host, performed by thememory system functioning as the sending-side SSD.

FIG. 10 is a block diagram for illustrating a garbage collectionoperation performed by the memory system functioning as the sending-sideSSD.

FIG. 11 is a view for illustrating the relationship between NAND memorychips and a NAND interface which are included in the memory systemfunctioning as the sending-side SSD.

FIG. 12 is a view for illustrating a duty-ratio control operationperformed by the memory system functioning as the sending-side SSD.

FIG. 13 is a view for illustrating an example of performance reductionnotification processing performed by the memory system functioning asthe sending-side SSD.

FIG. 14 is a view for illustrating another example of performancereduction notification processing performed by the memory systemfunctioning as the sending-side SSD.

FIG. 15 is a flowchart for illustrating a procedure of GC operation andperformance reduction notification processing performed by the memorysystem functioning as the sending-side SSD.

FIG. 16 is a flowchart for illustrating a procedure of thermalthrottling operation and performance reduction notification processingperformed by the memory system functioning as the sending-side SSD.

FIG. 17 is a flowchart for illustrating a procedure of power-constraintthrottling operation and performance reduction notification processingperformed by the memory system functioning as the sending-side SSD.

FIG. 18 is a block diagram for illustrating a configuration example of amemory system functioning as a receiver-side SSD.

FIG. 19 is a flowchart for illustrating a procedure of write performancereduction processing performed by the memory system functioning as thereceiver-side SSD when a performance reduction notification has beenreceived.

FIG. 20 is a flowchart for illustrating a procedure of a GC operationperformed by the memory system functioning as the receiver-side SSD whena performance reduction notification has been received.

FIG. 21 is a flowchart for illustrating a procedure of a throttlingoperation performed by the memory system functioning as thereceiver-side SSD when a performance reduction notification has beenreceived.

FIG. 22 is a block diagram for illustrating a configuration example of amemory system having both a function as a sending-side SSD and afunction as a receiver-side SSD.

FIG. 23 is a block diagram illustrating a configuration example of ahost.

FIG. 24 is a perspective view illustrating a configuration example of acomputer that includes both the memory system of the embodiment and thehost.

DETAILED DESCRIPTION

Various embodiments will be described hereinafter with reference to theaccompanying drawings.

In general, according to one embodiment, a memory system is configuredto operate as one of semiconductor storage devices in a storage array inwhich data is distributed across the semiconductor storage devices. Thememory system includes a nonvolatile memory and a controllerelectrically connected to the nonvolatile memory. The controllerexecutes a write operation of writing data, received from a host, to thenonvolatile memory.

The controller receives, from the host or another semiconductor storagedevice in the storage array, a notification indicative of a valuerelated to an amount of reduction in write performance of the anothersemiconductor device. The controller reduces performance of the writeoperation based on the value notified by the received notification.

Referring first to FIG. 1, a configuration of an information processingsystem 1 comprising the memory system according to one embodiment isdescribed.

This memory system is a semiconductor storage device configured to writedata to a nonvolatile memory, and to read data from the nonvolatilememory. For instance, the memory system may be realized as a solid statedrive (SSD) 3 including NAND flash memories.

The information processing system 1 comprises a host (host device) 2 anda storage array (SSD array). The SSD array includes plural semiconductorstorage devices (SSDs). The SSD array is configured to distribute dataacross SSDs. The SSD array may be realized by a RAID array, such as RAIDlevel 0, RAID level 5 or RAID level 6.

The SSD 3 of the embodiment can function as one semiconductor storagedevice (SSD) in the SSD array. Only one SSD in the SSD array may berealized by the SSD 3 of the embodiment, or all SSDs in the SSD arraymay be each realized by the SSD 3 of the embodiment. FIG. 1 shows anexample case where all SSDs in the SSD array are each realized by theSSD 3 of the embodiment.

In this SSD array, data is distributed across SSDs by striping. The datato be written to the SSD array by the host 2 may be divided into aplurality of data blocks each having a certain size, and these datablocks may be distributed across the SSDs 3 by striping.

If the SSD array is realized by RAID level 5 or 6, data with a parityblock is distributed across the SSDs 3 by striping.

A description will be mainly given of a case where the SSD is a RAIDarray corresponding to RAID level 0 (striping), although the SSD is notlimited to it.

In FIG. 1, a case where the SSD array comprises four SSDs 3 (SSD#1,SSD#2, SSD#3, SSD#4 ) is assumed.

The data to be written by the host 2 to the SSD array may be dividedinto four data blocks Data#1, Data#2, Data#3 and Data#4. These datablocks Data#1, Data#2, Data#3 and Data#4 may be transmitted from thehost 2 to SSD#1 , SSD#2, SSD#3 and SSD#4, respectively. SSD#1, SSD#2,SSD#3 and SSD#4 may simultaneously write data blocks Data#1, Data#2,Data#3 and Data#4, respectively. Data blocks Data#1, Data#2, Data#3 andData#4 constitute one stripe.

After four data blocks Data#1, Data#2, Data#3 and Data#4 are written,subsequent four data blocks Data#5, Data#6, Data#7 and Data#8 may betransmitted from the host 2 to SSD#1, SSD#2, SSD#3 and SSD#4,respectively. SSD#1, SSD#2, SSD#3 and SSD#4 may simultaneously writedata blocks Data#5, Data#6, Data#7 and Data#8, respectively.

The host 2 is an information processing apparatus, such as a server or apersonal computer. Each SSD 3 in the SSD array may be built in theinformation processing apparatus, or may be connected to the informationprocessing apparatus through a cable or a network.

As an interface for interconnecting the host 2 and each SSD 3, SCSI,Serial Attached SCSI (SAS), ATA, Serial ATA (SATA), PCI Express (PCIe),etc., can be used.

To efficiently operate the SSD array, it is desirable to make the SSDsto cooperate with each other. To this end, there is a demand forrealization of a new mechanism for the cooperative operation.

The SSD 3 of the embodiment may function as either sending-side SSD orthe receiving-side SSD. The sending-side SSD means an SSD having afunction of notifying the host 2 or the other SSDs in the SSD array of avalue related to an amount of reduction in the write performance of thesending-side SSD itself. The receiving-side SSD means an SSD having afunction of receiving from the sending-side SSD or the host 2, dataindicating a value related to an amount of reduction in the writeperformance of the sending-side SSD, and a function of reducing its ownwrite performance in accordance with the value related to the amount ofreduction in the write performance of the sending-side SSD.

The write performance of the SSD 3 may fall because of an internaloperation for managing the SSD 3. Typical internal operations include agarbage collection operation, a thermal protection operation (such asthermal throttling) for preventing excessive heating of the SSD 3, apower restriction operation (such as power restriction throttling) forsuppressing the power consumption of the SSD 3 equal to or less than amaximum power allowed to the SSD 3.

The write performance of the SSD 3 means the performance of a writeoperation of writing data from the host 2 to a nonvolatile memory in theSSD 3. This write performance may be expressed in terms of writethroughput. The write throughput is an amount of data that can betransmitted per unit time from the host 2 to the SSD 3, i.e., a datatransfer rate.

Assume here a case where SSD#2 functions as the sending-side SSD.

When it is assumed that the write performance (write throughput) ofSSD#2 has been reduced by the start of an internal operation of SSD#2,SSD#2 estimates a value related to an amount of reduction in the writeperformance of SSD#2 based on the content of the internal operation, andnotifies the host 2 or the other SSDs in the SSD array of the estimatedvalue related to the amount of reduction in the write performance. Theestimated value may be a reduced write performance after start of theinternal operation, or an amount itself of reduction in the writeperformance. For instance, if it is estimated that the write performanceof SSD#2 has been reduced from normal write performance (of, forexample, a transfer rate of 1 Gbyte/s) assumed when no internaloperation is performed, to a transfer rate of 512 Mbytes/s), SSD#2 maynotify the host 2 or the other SSDs in the SSD array that the writeperformance of SSD#2 has reduced to 512 Mbytes/s, in order to set allSSDs of the SSD array to 512 Mbytes/s.

Each SSD notified of the above by the host 2 or the sending-side SSD canreduce its write performance based on the notified value (writeperformance reduction amount).

For example, each SSD having received this notification may performcontrol for reducing its own write performance to the reduced writeperformance (in this case, 512 Mbytes/s) designated by the notification.If, for example, each SSD having received the notification has a writeperformance of 1 Gbyte/s, it may reduce its own write performance (writerate) to 512 Mbytes/s, thereby reducing its consumption of energy.Alternatively, each SSD may reduce its own write performance to 512Mbytes/s, and may perform a garbage collection operation in advance,using the remaining write performance (in this case, 512 Mbytes/s).

Thus, the notification function of the sending-side SSD enableseffective use of its write performance reduced period for reducing thepower consumption of the other SSDs or for causing the other SSDs toperform a garbage collection operation in advance.

As a method of notifying the host 2 of a value related to an amount ofreduction in the write performance of the sending-side SSD, an arbitrarymethod that enables the sending-side SSD to notify the host 2 of itswrite performance reduction amount can be used. For example, whenstarting an internal operation, the sending-side SSD may transmit aninterrupt signal to the host 2, thereby notifying the host 2 of thewrite performance reduction amount of the sending-side SSD. If the host2 has a function of periodically reading the internal register of thesending-side SSD, the sending-side SSD may set its write performancereduction amount in the internal register.

Upon receiving data indicating the write performance reduction amountfrom the sending-side SSD, the host 2 may notify each SSD in the SSDarray of the write performance reduction amount. Alternatively, uponreceiving data indicating the write performance reduction amount fromthe sending-side SSD, the host 2 may execute control for reducing thewrite performance of the other SSDs in the SSD array, based on thenotified write performance reduction amount.

The value related to an amount of reduction in the write performance ofthe sending-side SSD may be directly notified to the other SSDs of theSSD array, without using the host 2 (host CPU). As a method for thistype notification, an arbitrary method that enables direct communicationbetween SSDs without the host 2 can be used. For example, when each SSDin the SSD array is electrically connected to the host 2 through a PCIExpress (PCIe) bus, communication (end-to-end communication) between thesending-side SSD and each of the other SSDs may be performed through abus switch for connecting PCIe buses.

Further, in a case where an array configuration wherein each SSD iselectrically connected to the host 2 through an array controller (forexample, a RAID controller) 2A as shown in FIG. 2 is used, communicationbetween the sending-side SSD and each of the other SSDs may be performedthrough the array controller 2A.

The array controller 2A performs control for distributing, across theSSDs by striping, write data received from the host 2. The arraycontroller 2A may be realized by a RAID controller.

FIG. 3 shows an example of a write operation of the SSD array.

Assume here that the SSD array includes four SSDs SSD#1 to SSD#4.

The host 2 or the array controller 2A may divide data of a particularsize (for example, 128K bytes) into four data blocks (each block has asize of 32 Kbytes), and may cause SSD#1 to SSD#4 to write the four datablocks in a parallel way.

For example, the host 2 or the array controller 2A transmits writecommands and data blocks to the four SSDs 3 at time T10. In this case,the first data block of 32 Kbytes included in data of 128 Kbytes istransmitted as write data to SSD#1. The second data block of 32 Kbytesincluded in the data of 128 Kbytes is transmitted as write data toSSD#2. The third data block of 32 Kbytes included in the data of 128Kbytes is transmitted as write data to SSD#3. The last data block of 32Kbytes included in the data of 128 Kbytes is transmitted as write datato SSD#4.

SSD#1 to SSD#4 write the received data blocks to the respectivenonvolatile memories in SSD#1 to SSD#4. After SSD#1 to SSD#4 completedata writing, the host 2 or the array controller 2A sequentiallytransmits, at time T11, write commands and data blocks included insubsequent data of 128K bytes. In this case, a first block of 32 Kbytesincluded in the subsequent data of 128 Kbytes is transmitted as writedata to SSD#1. A second block of 32 Kbytes included in the subsequentdata of 128 Kbytes is transmitted as write data to SSD#2. A third blockof 32 Kbytes included in the subsequent data of 128 Kbytes istransmitted as write data to SSD#3. A last block of 32 Kbytes includedin the subsequent data of 128 Kbytes is transmitted as write data toSSD#4.

FIG. 4 shows examples of write operations performed in the SSD arraywhen a certain SSD in the SSD array has reduced in write performance.

In FIG. 4, a case where the write operation of SSD#2 is not completed atscheduled time T11 because of a reduction in the write performance ofSSD#2 is assumed.

At time T11, the host 2 or the array controller 2A can transmit, toSSD#1, the first data block of the subsequent data of 128K bytes.

However, since SSD#2 is in a busy state in which a write operation isprogressing, it cannot start a subsequent write operation. In this case,transmission of a subsequent data block from the host 2 or the arraycontroller 2A to SSD#2 may be stalled until the current write operationof SSD#2 is completed. Since thus, SSD#2 may become a bottleneck,transmission of data blocks from the host 2 or the array controller 2Ato SSD#3 and SSD#4 may be also stalled.

After SSD#2 completes the data write operation, the host 2 or the arraycontroller 2A sequentially transmits, to SSD#2, SSD#3 and SSD#4 , writecommands and data blocks in the subsequent data of 128 Kbyte. The seconddata block of 32 Kbytes included in the subsequent data of 128 Kbytes istransmitted as write data to SSD#2. The third data block of 32 Kbytesincluded in the subsequent data of 128 Kbytes is transmitted as writedata to SSD#3. The last data block of 32 Kbytes included in thesubsequent data of 128 Kbytes is transmitted as write data to SSD#4.

Therefore, during a period between times T11 and T12, SSD#3 and SSD#4may be maintained in an idle state with no work loads to be executed.

Transmission of a subsequent data block from the host 2 or the arraycontroller 2A to SSD#1 may be stalled until the write operation of SSD#4is completed. Therefore, SSD#1 may be maintained in an idle state duringa period between times T12 and T13.

Thus, the write performance for writing data from the host 2 (i.e., thewrite performance of the SSD array) may be limited by the reduced writeperformance of SSD#2.

FIG. 5 shows a garbage collection (GC) operation performed by other SSDsin the SSD array during a period in which the write performance of SSD#2is reduced.

As described above, SSD#2 can function as the sending-side SSD.Therefore, when the write performance of SSD#2 has reduced, SSD#2 cannotify the host 2 or the other SSDs in the SSD array of a value relatedto an amount of reduction in the write performance of SSD#2.

This enables, for example, each of SSD#1, SSD#3 and SSD#4 to perform agarbage collection (GC) operation in advance during the period betweentimes T11 and T12 in which the SSD#1, SSD#3 and SSD#4 waiting for thecompletion of the write operation of SSD#2.

The execution of a garbage collection (GC) operation in advance meansstarting of a garbage collection (GC) operation before the number ofremaining free blocks is less than or equal to a threshold at which thegarbage collection (GC) operation should be started. Since thus, thenumber of free blocks in each of SSD#1, SSD#3 and SSD#4 can be increasedearly, SSD#1, SSD#3 and SSD#4 can delay the start time of a subsequentGC operation. Accordingly, the time of write performance reduction ofeach of SSD#1, SSD#3 and SSD#4 due to the start of the garbagecollection (GC) operation can be delayed.

FIG. 6 shows write operations and garbage collection (GC) operationsperformed by other SSDs in the SSD array during a period in which thewrite performance of SSD#2 is reduced.

FIG. 5 is directed to the case where each of SSD#1, SSD#3 and SSD#4performs a garbage collection (GC) operation during the period betweentimes T11 and T12. In contrast, in FIG. 6, each of SSD#1, SSD#3 andSSD#4 performs a write operation of data received from the host 2 and agarbage collection (GC) operation in parallel during the period rangingfrom time T10 to time T12.

For example, when SSD#1 to SSD#4 are operating at a write performance of1 Gbyte/s, if the write performance of SSD#2 falls to 512 Mbytes/s, eachof SSD#1, SSD#3 and SSD#4 may perform the write operation of writingdata from the host 2 and the garbage collection (GC) operation inparallel, by using a write performance of 512 Mbytes/s for the writeoperation and using the remaining performance of 512 Mbytes/s for thegarbage collection (GC) operation.

FIG. 7 shows throttling operations performed by other SSDs in the SSDarray during a period in which the write performance of SSD#2 isreduced.

The throttling operation means an operation of restricting writeperformance. For instance, an example of the throttling operation is asfollows:

(1) The number of nonvolatile memory chips to be simultaneously (inparallel) driven is restricted.

(2) The ratio (duty ratio) of a first period to one cycle that includesthe first period in which a plurality of nonvolatile memories aresimultaneously (in parallel) driven, and a second period in which aplurality of nonvolatile memories are not driven is restricted.

(3) The number of nonvolatile memories to be simultaneously driven(driven in parallel) is restricted, and the duty ratio is restricted.

In the period ranging from time T10 to time T12, SSD#1, SSD#3 and SSD#4reduce their write performance to the same level as the reduced writeperformance of SSD#2 by executing respective throttling operations.

In general, as increasing the write throughput of an SSD, the powerconsumption of the SSD is increased. Accordingly, by reducingperformance of the write operation of each of SSD#1, SSD#3 and SSD#4,the power consumption of them can be reduced.

Thus, in the embodiment, the sending-side SSD transmits, to the host 2or the other SSDs, a value (e.g., the level of the reduced writeperformance) corresponding to an amount of reduction in writeperformance, instead of data indicating, for example, the number ofremaining free blocks. As a result, the write performance of each of theother SSDs can be easily reduced to the same level as the reduced writeperformance of the sending-side SSD, whereby the write performance ofall SSDs in the SSD array can be efficiently balanced, without anyparticular processing by the host 2.

FIG. 8 shows a configuration example of the SSD 3 that functions as theabove-mentioned sending-side SSD.

The SSD 3 includes a controller 4 and a nonvolatile memory (NAND memory)5. The SSD 3 may further include a random-access memory such as a DRAM6, and a temperature sensor 7. The NAND memory 5 may comprise aplurality of NAND memory chips (nonvolatile memory chips).

The NAND memory 5 includes a large number of NAND blocks (blocks) B0 toBm-1. Each of blocks B0 to Bm-1 function as the unit of erase. Eachblock may also be called a physical block or an erase block.

Blocks B0 to Bm-1 each include a large number of pages (physical pages).Specifically, each of blocks B0 to Bm-1 includes pages P0 to Pn-1. Inthe NAND memory 5, a data read and a data write are performed in unitsof a page. A data erase is performed in units of a block.

The controller 4 is electrically connected to the NAND memory 5 as anonvolatile memory through a NAND interface 13, such as a toggle orONFI. The NAND interface 13 may have a plurality of channels. Eachchannel is connected to some NAND memory chips. The controller 4 cancause the NAND memory chips connected to the NAND interface 13 toperform write and read operations in parallel.

The controller 4 may function as a flash translation layer (FTL)configured to perform data management and block management of the NANDmemory 5.

The data management includes, for example, (1) management of mappinginformation indicative of the relationship between logical blockaddresses (LBAs) and physical addresses, and (2) processing of hiding apage-unit read/write operation and a block-unit erase operation. Themapping management between LBAs and physical addresses is performedusing a look-up table (LUT) 33 that functions as a logical-to-physicaladdress translation table. The look-up table (LUT) 33 manages mappingbetween the LBAs and the physical addresses in units of a particularmanagement size. Many of the write commands from the host 2 request adata write of 4 Kbytes. Therefore, the look-up table (LUT) 33 may managemapping between LBAs and physical addresses in units of, for example, 4Kbytes. A physical address corresponding to a certain LBA indicates aphysical storage location in the NAND memory 5, where the data of thisLBA was written. The physical address includes a physical block addressand a physical page address. The physical page address is allocated toeach of all pages, and the physical block address is allocated to eachof all physical blocks.

Data write to the page is possible only once per erase cycle.

Accordingly, the controller 4 maps write (overwrite) to a certain LBA toanother page in the NAND memory 5. That is, the controller 4 writes thisdata to this another page. Further, the controller 4 updates the look-uptable (LUT) 33 and associates this LBA with this another page, and alsoinvalidates the original page (the old data with which this LBA has beenassociated).

The block management includes a bad block management, wear leveling,garbage collection, etc. The wear leveling is an operation of levelingthe program/erase cycles (i.e., erase counts) among the physical blocks.

The garbage collection is an operation for creating a free space in theNAND memory 5. The garbage collection operation copies all valid data inseveral blocks in which the valid data and invalid data are mixed toanother block (copy destination free block), in order to increase thenumber of free blocks in the NAND memory 5. Valid data is newest dataassociated with a certain LBA. Invalid data is data that is no longerused by the host 2 by updating or erasure, i.e., old data associatedwith no LBAs. The garbage collection operation updates the look-up table(LUT) 33, thereby associating the LBAs of the copied valid data withrespective correct physical addresses. A block, which includes only theinvalid data after the valid data has been copied to another block,becomes a free block. Thus, this block can be reused after erasing thisblock.

The host 2 transmits a write command to the SSD 3. This write commandcontains the logical address (starting logical address) of write data(namely, data to be written), and the transfer length of the write data.Although in the embodiment, the LBA is used as the logical address,object ID may be used as the logical address in another embodiment. TheLBA is expressed by the serial number allocated to a logical sector(logical block). The serial number begins with zero. The size of thelogical sector is, for example, 512 bytes.

The controller 4 of the SSD 3 writes write data, which is designated bythe starting logical address and transfer length in the write command,to a page of a block in the NAND memory 5. Further, the controller 4updates the look-up table (LUT) 33, thereby associating the LBA, whichcorresponds to the written data, with the physical address indicatingthe physical storage location at which the data was written.

More specifically, the controller 4 allocates one of the free blocks inthe NAND memory 5 for writing data from the host 2. The allocated blockis a write target block to which the data from the host 2 is to bewritten, and is also called “a write destination block” or “an inputblock.” While updating the look-up table (LUT) 33, the controller 4successively writes data, received from the host 2, to available pagesin the write target block (write destination block). When the writetarget block has no more available page, the controller 4 allocates anew free block as a write target block.

Next, a configuration of the controller 4 will be described.

The controller 4 may include a host interface 11, a CPU 12, a NANDinterface 13, a DRAM interface 14, an SRAM 15, etc. The CPU 12, the NANDinterface 13, the DRAM interface 14 and the SRAM 15 may be connected toeach other via a bus 10. The host interface 11 receives various commands(a write command, a read command, an UNMAP command, etc.) from the host2.

The write command requests the SSD 3 to write data designated by thewrite command. The write command contains the LBA (starting LBA) of afirst logical block to be written, and a transfer length (the number oflogical blocks). The read command requests the SSD 3 to read datadesignated by the read command. The read command contains the LBA(starting LBA) of a first logical block to be read, and a transferlength (the number of logical blocks).

The CPU 12 is a processor configured to control the host interface 11,the NAND interface 13, the DRAM interface 14 and the SRAM 15. Inaddition to the above-mentioned FTL processing, the CPU 12 performscommand processing for processing various commands from the host 2.

For example, upon receiving a write command from the host 2, thecontroller 4 performs a write operation of writing data designated bythe write command to the NAND memory 5 under control of the CPU 12, asdescribed below.

That is, the controller 4 writes data to a physical storage location(available page) in a current write target block, and updates thelook-up table (LUT) 33, thereby associating the physical address of thephysical storage location with the LBA (starting LBA) included in thewrite command.

The FTL processing and the command processing may be controlled byfirmware executed by the CPU 12. The firmware causes the CPU 12 tofunction as a garbage collection (GC) operation control unit 21, athermal protection throttling control unit 22, a power-restrictionthrottling control unit 23, and a write performance reductionnotification unit 24.

The garbage collection operation control unit 21 performs a garbagecollection operation of copying valid data in some blocks (fragmentedblocks) selected as garbage collection targets to another block (copydestination block). The garbage collection operation is performed, forexample, when the number of free blocks in the NAND memory 5 becomes aparticular threshold or less. The garbage collection operation consumesthe resources of the SSD 3 and degrades the performance of the SSD 3.Therefore, during execution of the garbage collection operation, theperformance of the write operation to write data received from the host2 to a write target block (i.e., write performance) may be degraded.

The thermal protection throttling control unit 22 performs a thermalprotection operation (thermal throttling operation) for preventingoverheating of the SSD 3 based on a temperature detected by thetemperature sensor 7. The thermal throttling operation is realized byrestricting the write performance of the SSD 3. More specifically, basedon the temperature detected by the temperature sensor 7, the thermalprotection throttling control unit 22 restricts the number of NANDmemory chips simultaneously driven (driven in parallel), or restrictsthe ratio of a first period in which a plurality of NAND memory chipsare simultaneously driven, to one cycle that includes the first periodand a second period in which the NAND memory chips are not driven.

The power-restriction throttling control unit 23 performs a powerrestriction operation (power-restriction throttling operation) ofrestricting the power consumption (energy consumption) of the SSD 3 toor less than maximum power allowable to the SSD 3. The maximum powerallowable to the SSD 3 may be beforehand notified to the SSD 3 by thehost 2. The maximum power indicates a maximum power consumption allowedto the SSD 3.

The power-restriction throttling operation can also be performed byrestricting the write performance of the SSD 3. More specifically, basedon the maximum power allowed to the SSD 3 and the power consumption ofeach NAND memory chip, the power-restriction throttling control unit 23restricts the number of NAND memory chips to be simultaneously driven(driven in parallel) or restricts the ratio of a first period in whichthe NAND memory chips are simultaneously driven (driven in parallel), toone cycle that includes the first period and a second period in whichthe NAND memory chips are not driven.

When an internal operation (the garbage collection operation, thethermal throttling operation or the power-restriction throttlingoperation) is started, the write performance reduction notification unit24 estimates a value related to an amount of reduction in the writeperformance of the sending-side SSD due to the start of the internaloperation, based on content of the started internal operation. Then, thewrite performance reduction notification unit 24 notifies the host 2 orone or more of the other SSDs in the SSD array of the estimated valuerelated to the amount of reduction in the write performance.

The estimated value may be a reduced write performance, i.e.,performance obtained after the performance of the write operation hasreduced because of start of the internal operation. In this case, if,for example, the write performance has reduced from 1 Gbyte/s to 500Mbytes/s, 500 Mbytes/s may be estimated as the value related to theamount of reduction in the write performance.

Alternatively, the value related to the amount of reduction in the writeperformance may be the amount itself of reduction in the writeperformance, namely, a value obtained by subtracting the reduced writeperformance from a normal write performance. The normal writeperformance is a write performance before start of the internaloperation. In this case, if, for example, the write performance hasreduced from 1 Gbyte/s to 500 Mbytes/s, 524 Mbytes/s (=1024−500) may beestimated the value related to the amount of reduction in the writeperformance.

When the write performance has been recovered by the end of the internaloperation, the write performance reduction notification unit 24 maynotify the host 2 or one or more of the other SSDs in the SSD array thatthe write performance has been recovered to the normal write performance(e.g., 1 Gbyte/s).

Next, other components in the controller 4 will be described.

The NAND interface 13 is a NAND controller configured to control theNAND memory 5 under control of the CPU 12. The NAND interface 13 may beof multichannel, for example, may include eight channels (CH#1 to CH#8).Each channel includes a bus for transmitting data, commands andaddresses.

The DRAM interface 14 is a DRAM controller configured to control theDRAM 6 under control of the CPU 12.

The memory area of the DRAM 6 may be used as a write buffer (WB) 31 fortemporarily storing data to be written to the NAND memory 5. The memoryarea of the DRAM 6 may also be used as a GC buffer 32 for temporarilystoring data moved during a garbage collection (GC) operation. Thememory area of the DRAM 6 may further be used for storing theabove-mentioned look-up table 33.

The SSD 3 may further hold other various management data items. As anexample of the management data, a page management table holdingvalid/invalid flags corresponding to respective physical addresses maybe included. Each valid/invalid flag indicates whether the correspondingphysical address (e.g., physical page) is valid or invalid. The validphysical page means that the data therein is valid data. The invalidphysical page means that the data therein is invalided by updating(rewriting).

Next, the configuration of the host 2 will be described.

The host 2 is an information processing apparatus for executing variousprograms. The programs executed by the host 2 include an applicationsoftware layer 41, an operating system (OS) 42 and a file system 43.

As generally known, the operating system (OS) 42 is software configuredto manage the entire host 2, control the hardware in the host 2, andenable applications to use the hardware and the SSD 3.

The file system 43 is used for controlling the operation (creation,saving, update, deletion, etc.) of a file. For instance, ZFS, Btrfs,XFS, ext4, NTFS, etc., may be used as the file system 43. Alternatively,a file object system (such as Ceph Object Memory Daemon) or a key valuestore system (for example, Rocks DB) may be used as the file system 43.

Various application software threads run on the application softwarelayer 41. Examples of the application software threads are clientsoftware, database software, virtual machine, etc.

When the application software layer 41 needs to send a request, such asa read command or a write command, to the SSD 3, it sends the request tothe OS 42. The OS 42 sends that request to the file system 43. The filesystem 43 translates that request into a command (a read command, awrite command, etc.). The file system 43 sends the command to the SSD 3.Upon receiving a response from the SSD 3, the file system 43 sends thatresponse to the OS 42. The OS 42 sends that response to the applicationsoftware layer 41.

The host 2 may further include a device performance manager 44. Thedevice performance manager 44 receives a notification of performancereduction from a certain SSD in the SSD array, and transmits thenotification of performance reduction to each of the other SSDs in theSSD array.

FIG. 9 shows an operation of successively allocating free blocks forwriting data received from the host 2.

The controller 4 allocates, as a write target block 62, one of the freeblocks listed in a free block list 60.

The controller 4 writes, to the write buffer 31, write data receivedfrom the host 2. After that, while updating the look-up table (LUT) 33,the controller 4 sequentially writes the write data in the write buffer31 to the write target block 62, from the first page toward the lastpage of the block 62.

If the write target block 62 does not have any more available page, thecontroller 4 manages the write target block 62 as an active block (blockcontaining data). Therefore, the controller 4 moves the write targetblock 62 to an active block list 61. After that, the controller 4allocates a free block in the free block list 60 as a new write targetblock 62.

If all data of a block included in the active block list 61 isinvalidated by its updating, this block is moved to the free block list60.

If the number of free blocks in the free block list 60 decreases to avalue equal to or less than a particular threshold, the above-mentionedgarbage collection (GC) operation is performed for creating a freeblock.

FIG. 10 shows the garbage collection (GC) operation performed by thecontroller 4.

More specifically, FIG. 10 shows an example case where four blocks B11,B12, B13 and B14 are selected as of GC operation targets. The controller4 selects some blocks to be set GC operation targets from blocks inwhich valid data (valid pages) and invalid data (invalid pages) aremixed. The controller 4 may refer to the above-mentioned page managementtable that holds valid/invalid flags corresponding to the respectivephysical addresses, thereby preferentially selecting, as GC operationtargets, blocks that contain larger amounts of invalid data. Thecontroller 4 copies the valid data of the GC operation target blocks toat least one copy destination block.

The number of copy destination blocks required for the GC operation isdetermined based on the amount of valid data to be copied by the GCoperation. FIG. 10 shows a case where two free blocks are set as copydestination blocks B101 and B102.

Copy destination block B101 and B102 are filled with valid data. BlockB11, B12, B13 and B14 become free blocks which do not contain validdata.

Blocks B11, B12, B13 and B14 that have become to free blocks are movedto the free block list 60.

FIG. 11 shows the relationship between the NAND interface 13 and aplurality of NAND memory chips.

More specifically, FIG. 11 shows an example case where four NAND memorychips are connected to each of eight channels (CH#1 to CH#8) included inthe NAND interface 13. The NAND interface 13 can change, under controlof the controller 4, the number of NAND memory chips to besimultaneously driven (driven in parallel) per channel.

If the number of NAND memory chips simultaneously driven per channel isset to 4, the total number of NAND memory chips simultaneously driven(by a parallel operation) is 32 (that realizes maximum writeperformance).

If the number of NAND memory chips simultaneously driven per channel isset to 3, the total number of NAND memory chips simultaneously driven(by a parallel operation) is 24 (that realizes 75% of the maximum writeperformance).

If the number of NAND memory chips simultaneously driven per channel isset to 2, the total number of NAND memory chips simultaneously driven(by a parallel operation) is 16 (that realizes 50% of the maximum writeperformance).

If the number of NAND memory chips simultaneously driven per channel isset to 1, the total number of NAND memory chips simultaneously driven(by a parallel operation) is 8 (that realizes 25% of the maximum writeperformance).

By thus changing the number (total) of NAND memory chips simultaneouslydriven (by a parallel operation), the write performance, powerconsumption and thermal generation of the SSD 3 can be adjusted.

FIG. 12 shows a duty control operation.

In a write operation of writing data to the NAND memory 5, thethirty-two NAND memory chips may be intermittently driven. The cycle(duty width) of intermittent driving includes an ON period in which awrite operation is performed, and an OFF period in which no writeoperation is performed.

In the ON period, the thirty-two NAND memory chips may be allsimultaneously driven (by a parallel operation). At this time, each NANDmemory chip assumes a busy state where a write operation is advancing.

In the OFF period, none of the thirty-two NAND memory chips is driven.At this time, each NAND memory chip assumes an idle state where no writeoperation is performed.

By controlling the ratio of the ON period to one cycle, the writeperformance, power consumption and thermal generation of the SSD 3 canbe adjusted. For example, if the ON period is set to one second when onecycle (duty width) is ten seconds (duty ratio=10%), the writeperformance of the SSD 3 is restricted to 10% of the maximum writeperformance. At this time, the mean power consumption of the SSD 3 forten seconds is 1/10 of the power consumption at the time of the maximumwrite performance.

FIG. 13 shows an example of performance reduction notificationprocessing executed by a sending-side SSD.

The controller 4 of SSD#2, which functions as the sending-side SSD,starts processing (above-mentioned internal operation) that is thefactor of write performance reduction, when necessary (step S11). Instep S11, the controller 4 estimates a value related to an amount ofreduction in the write performance of SSD#2, and transmits, to the host2, a notification of the write performance reduction of SSD#2. Thenotification of the performance reduction includes the estimated value(for example, a write performance after the reduction, or an amount ofreduction in the write performance) and factor data. The factor dataindicates whether the factor of the write performance reduction is thegarbage collection (GC) operation, the thermal throttling operation, orthe power-restriction throttling operation.

Upon receiving, from SSD#2, the notification of the write performancereduction, the host 2 transmits the notification to SSD#1, SSD#3 andSSD#4. Each of SSD#1, SSD#3 and SSD#4 functions as a receiving-side SSDconfigured to reduce its own write performance to the received, reducedwrite performance. The controller of SSD#1 performs processing ofreducing its own write performance to the received, reduced writeperformance (step S12). In step S12, the controller of SSD#1 may performa GC operation within a range in which the write performance of SSD#1 isnot less than the received, reduced write performance. Alternatively,the controller of SSD#1 may perform a throttling operation ofrestricting the number of NAND memory chips simultaneously driven or theabove-mentioned duty ratio within a range in which the write performanceof SSD#1 is not less than the received, reduced write performance.Further, the controller of SSD#1 may determine either the GC operationor the throttling operation, based on the received factor data.

For example, if the received factor data indicates the GC operation orpower restriction (throttling operation), the controller of SSD#1 mayperform either the GC operation or the throttling operation.

In contrast, if the factor of the write performance reduction is“thermal protection for preventing overheating” (thermal throttlingoperation), the controller of SSD#1 reduces own write performance not bythe GC operation but by the throttling operation. Thus, an excessivetemperature increase of the whole SSD array can be suppressed.

Similarly, SSD#3 and SSD#4 perform processing of reducing their ownwrite performance to the received, reduced write performance (steps S13and S14).

FIG. 14 shows another example of performance reduction notificationprocessing executed by the sending-side SSD.

The controller 4 of SSD#2 that functions as the sending-side SSD startsprocessing (above-mentioned internal operation) leading to writeperformance reduction of SSD#2, when necessary (step S21). In step S21,the controller 4 estimates a value related to an amount of reduction inthe write performance of SSD#2, and transmits a notification of thewrite performance reduction, to SSD#1, SSD#3 and SSD#4. The notificationof the performance reduction includes the estimated value (for example,write performance after the reduction, or an amount of reduction in thewrite performance), and the above-mentioned factor data.

SSD#1, SSD#3 and SSD#4 each perform processing of reducing their ownwrite performance to the received, reduced write performance (steps S22,S23 and S24).

The flowchart of FIG. 15 shows the procedure of a GC operation and aperformance reduction notification operation performed by thesending-side SSD.

The controller 4 of the sending-side SSD periodically checks the numberof remaining free blocks (step S31), and determines whether the numberof remaining free blocks is equal to or less than a threshold (stepS32).

If the number of remaining free blocks is equal to or less than thethreshold (YES in step S32), the controller 4 selects, as GC targetblocks (GC candidates), some blocks having greater amounts of invaliddata (step S33). Based on the amount of data to be copied during the GCoperation, namely, the amounts of valid data of respective GC targetblocks, the controller 4 estimates the write performance of thesending-side SSD during the GC period (step S34). In step S34, a valuerelated to an amount of reduction in the write performance of thesending-side SSD is estimated based on the amount of data to be copiedduring the GC operation. The value may indicate a reduced writeperformance (write performance after reduction due to the GC), or anamount of reduction in the write performance due to the GC.

The controller 4 sends, to the host 2 or the other SSDs in the SSDarray, a notification of performance reduction including the estimatedvalue (estimated write performance) and factor data (GC operation),thereby notifying the host 2 or the other SSDs in the SSD array that (1)the write performance of the sending-side SSD has reduced, (2) to whatdegree the write performance has reduced, and (3) why the writeperformance has reduced (step S35).

The controller 4 performs the GC operation of copying the valid data ofGC target blocks to a copy destination block, thereby increasing thenumber of free blocks (step S36). In step S36, the controller 4 mayexecute processing of writing write data (host data), received from thehost 2, to a write target block, and the GC operation in parallel. Inthis case, based on the amount of data needed to be copied for the GCoperation, the controller 4 may determine the ratio of the amount ofhost data which is to be written to the target write block, to theamount of data to be copied to the copy destination block for the GCoperation, and may execute host data writing processing and the GCoperation in parallel, based on the determined ratio.

If the GC operation has been completed (YES in step S37), the controller4 sends, to the host 2 or the other SSDs in the SSD array, anotification that the write performance of the sending-side SSD hasrecovered to the normal write performance (step S38). This notificationmay include a value (for example, 1 Gbyte/s) indicating the normal writeperformance.

The flowchart of FIG. 16 shows the procedure of the thermal throttlingoperation and performance-reduction notifying processing executed by thesending-side SSD.

The controller 4 of the sending-side SSD periodically checks thetemperature in the sending-side SSD detected by the temperature sensor7, and determines whether the detected temperature is not less thanthreshold T1 (step S41).

If the detected temperature is not less than threshold T1 (YES in stepS41), the controller 4 determines the number of NAND memory chips to besimultaneously driven, or the above-mentioned duty ratio (step S42).Based on the determined number of NAND memory chips or the determinedduty ratio, the controller 4 estimates the write performance of thesending-side SSD during a temperature protection period (namely, duringthe thermal throttling operation) (step S43). In step S43, a valuerelated to an amount of reduction in the write performance of thesending-side SSD is estimated based on the determined number of NANDmemory chips or the determined duty ratio. The value may indicate areduced write performance (write performance after reduction due to thethermal throttling operation), or an amount of reduction in the writeperformance due to the thermal throttling operation.

The controller 4 sends, to the host 2 or the other SSDs in the SSDarray, a notification of performance reduction including the estimatedvalue (estimated write performance) and factor data (thermal throttlingoperation), thereby notifying the host 2 or the other SSDs in the SSDarray that (1) the write performance of the sending-side SSD hasreduced, (2) to what degree the write performance has reduced, and (3)why the write performance has reduced (step S44).

The controller 4 starts a thermal throttling operation by restrictingthe number of currently simultaneously driven NAND memory chips or thecurrently-used duty ratio, based on the determination in step S42 (stepS45). By this thermal throttling operation, the calorific value of thesending-side SSD is reduced.

The controller 4 periodically checks the temperature in the sending-sideSSD detected by the temperature sensor 7, and determines whether thedetected temperature is not more than threshold T2 (step S46). ThresholdT2 may be set lower than threshold T1.

If the detected temperature is not more than threshold T2 (YES in stepS46), the controller 4 finishes the thermal throttling operation byreleasing the restriction of the number of simultaneously driven NANDmemory chips, or releasing the restriction of the duty ratio (step S47).After that, the controller 4 transmits, to the host 2 or the other SSDsin the SSD array, a notification of the recovery of the writeperformance of the sending-side SSD, thereby notifying the host 2 or theother SSDs in the SSD array that the write performance of thesending-side SSD has recovered to the normal write performance (stepS48). The notification of the recovery of the write performance mayinclude a value (for example, 1 Gbyte/s) indicating the normal writeperformance.

Although FIG. 16 is directed to the case of switching two operations(start of the thermal throttling operation and stop of the same) basedon the detected temperature, control of switching the number ofsimultaneously driven NAND memory chips or the duty ratio in multiplesteps based on the detected temperature may be executed instead. Forinstance, when the detected temperature has reduced to threshold T3between thresholds T1 and T2, the controller may re-determine the numberof NAND memory chips to be simultaneously driven or the duty ratio to beused, and may restrict the number of currently simultaneously drivenNAND memory chips or the current duty ratio, based on the re-determinednumber of NAND memory chips or the re-determined duty ratio. In thiscase, the controller 4 re-estimates a value related to an amount ofreduction in the write performance, based on the re-determined number ofNAND memory chips or the re-determined duty ratio, and may send, to thehost 2 or the other SSDs in the SSD array, a notification of performancereduction that includes the estimated value and factor data (thermalthrottling operation).

The flowchart of FIG. 17 shows the procedure of the power-restrictionthrottling operation and the performance-reduction notificationprocessing performed by the sending-side SSD.

The controller 4 of the sending-side SSD determines whether powerrestriction should be started, that is, whether a power-restrictionstart condition is satisfied, based on the relationship between thecurrent power consumption of the sending-side SSD and the maximum powerallowed to the sending-side SSD (step S51). The power consumption of thesending-side SSD is calculated as a function of the power consumption ofeach NAND memory chip and the number of simultaneously driven NANDmemory chips (or the duty ratio). If the power consumption of thesending-side SSD is greater than the maximum power allowed to thesending-side SSD by the host 2, the controller 4 determines the numberof simultaneously driven NAND memory chips, or the duty ratio, based onthe maximum power allowed to the sending-side SSD and the powerconsumption of each NAND memory chip (power consumption per chip), sothat the power consumption of the sending-side SSD becomes equal to orless than the maximum power (step S52).

Based on the determined number of simultaneously driven NAND memorychips, or the determined duty ratio, the controller 4 estimates thewrite performance of the sending-side SSD during a power restrictionperiod (power-restriction throttling period) (step S53). In step S53, avalue related to an amount of reduction in the write performance of thesending-side SSD is estimated based on the determined number of NANDmemory chips or the determined duty ratio. The value may indicate areduced write performance (write performance after reduction due to thepower-restriction throttling operation), or an amount of reduction inthe write performance due to the power-restriction throttling operation.

The controller 4 sends, to the host 2 or the other SSDs in the SSDarray, a notification of performance reduction including the estimatedvalue (estimated write performance) and factor data (power-restrictionthrottling operation), thereby notifying the host 2 or the other SSDs inthe SSD array that (1) the write performance of the sending-side SSD hasreduced, (2) to what degree the write performance has reduced, and (3)why the write performance has reduced (step S54).

The controller 4 starts a power-restriction throttling operation byrestricting the number of simultaneously driven NAND memory chips, orthe duty ratio, based on the determination result in step S52 (stepS55). By this power-restriction throttling operation, the powerconsumption of the sending-side SSD is reduced.

The host 2 may change the maximum power allowed to the sending-side SSD,when necessary. For example, if the host 2 requires an increase in thewrite performance of the whole SSD array, it may increase the maximumpower allowed to each SSD. In this case, the controller 4 determineswhether a condition for finishing power restriction is satisfied (stepS56).

If the condition is satisfied (YES in step S56), the controller 4finishes the power-restriction throttling operation by releasing therestriction of the number of simultaneously driven NAND memory chips, orthe restriction of the duty ratio (step S57). After that, the controller4 sends, to the host 2 or the other SSDs in the SSD array, anotification of recovery of the write performance of the sending-sideSSD, thereby notifying the host 2 or the other SSDs in the SSD arraythat the write performance of the sending-side SSD has recovered to thenormal write performance (step S58). The notification of the recovery ofthe write performance may include a value (for example, 1 Gbyte/s.)indicating the normal write performance.

Similarly, in order to reduce the power consumption of the informationprocessing system 1, the host 2 may reduce the maximum power allowed toeach SSD. In this case, the controller 4 re-determines the number ofNAND memory chips to be simultaneously driven or re-determines the dutyratio, based on the reduced maximum power allowed to the sending-sideSSD, and the power consumption of each NAND memory chip (powerconsumption per chip), so that the power consumption of the sending-sideSSD will be equal to or less than the reduced maximum power. Further,the controller 4 restricts the number of NAND memory chips currentlysimultaneously driven or the current duty ratio, based on there-determined number of simultaneously driven NAND memory chips or there-determined duty ratio. The controller 4 re-estimates a value relatedto an amount of reduction in the write performance, based on there-determined number of simultaneously driven NAND memory chips or there-determined duty ratio, and sends, to the host 2 or the other SSDs inthe SSD array, a notification of performance reduction that includes theestimated value and factor data (power-restriction throttlingoperation).

FIG. 18 shows a configuration example of the SSD 3 functioning as theabove-mentioned receiving-side SSD.

The receiving-side SSD comprises a write performance adjustment unit 25instead of the write performance reduction notification unit 24.

The write performance adjustment unit 25 receives, from host 2 oranother SSD, a notification that the write performance of said anotherSSD has reduced, and executes processing of reducing the writeperformance of the receiving-side SSD, based on the value related to anamount of reduction of the write performance, which is designated by thenotification, and the performance reduction factor designated by thenotification.

If the factor data included in the received notification is associatedwith a GC operation or a power-restriction throttling operation, thewrite performance adjustment unit 25 may perform the GC operation. Inthis case, the write performance adjustment unit 25 determines the ratioof the amount of write data from the host 2, which is to be written to awrite target block, to the amount of data to be copied to a copydestination block for the GC operation, based on the value related tothe amount of reduction of the write performance. Based on this ratio,the write performance adjustment unit 25 performs a GC operation usingthe garbage collection operation control unit 21.

For example, if the ratio of the amount of write data to the amount ofdata to be copied for the GC operation is 1 to 1, an operation ofcopying a particular amount of valid data from a GC target block to acopy destination block may be performed whenever this particular amountof write data is written to a write target block.

If factor data included in the received notification indicates thermalthrottling, the write performance adjustment unit 25 does not perform aGC operation, and reduces the write performance of the receiving-sideSSD by a throttling operation. In this case, the write performanceadjustment unit 25 determines the number of NAND memory chips to besimultaneously driven or the duty ratio to be used, based on the valueincluded in the received notification (e.g., reduced write performance),and restricts the number of currently simultaneously driven NAND memorychips or the current duty ratio, based on the determined number of NANDmemory chips or the determined duty ratio.

The flowchart of FIG. 19 shows the procedure of the write performancereduction processing performed by the receiving-side SSD.

When having received, from the host 2 or another SSD, a notificationthat the write performance of said another SSD has reduced (YES in stepS61), the controller 4 of the receiving-side SSD checks the factor ofthe write performance reduction of said another SSD, based on factordata included in the received notification (step S62).

If the factor of the write performance reduction of said another SSD isa GC operation (YES in step S63), the controller 4 of the receiving-sideSSD reduces its write performance to a level substantially equal to thereduced write performance of said another SSD, by performing a GCoperation in advance or performing a throttling operation (step S64).

If the factor of the write performance reduction of said another SSD isthermal protection (thermal throttling) (YES in step S65), thecontroller 4 of the receiving-side SSD reduces its write performance toa level substantially equal to the reduced write performance of saidanother SSD, by performing a throttling operation (step S66). At thistime, in order to prevent an excessive temperature rise, thereceiving-side SSD is inhibited from performing a GC operation inadvance.

If the factor of the write performance reduction of said another SSD ispower restriction (power restriction throttling) (YES in step S67), thecontroller 4 of the receiving-side SSD reduces its write performance toa level substantially equal to the reduced write performance of saidanother SSD, by performing a throttling operation (step S68).Alternatively, the controller 4 of the receiving-side SSD may perform aGC operation an advance within a range in which the power consumption ofthe receiving-side SSD will not depart from the maximum power allowedthereto.

In addition, when having received, from the host 2 or another SSD, anotification of the recovery of the write performance of said anotherSSD, the controller 4 of the receiving-side SSD performs processing ofrecovering the write performance of the receiving-side SSD to the normalwrite performance (for example, 1 Gbyte/s) by stopping the GC operationor the throttling operation.

The flowchart of FIG. 20 shows the procedure of a GC operation performedby the receiving-side SSD when a notification of performance reductionhas been received.

Based on the notified value related to the amount of reduction in thewrite performance of the sending-side SSD, the controller 4 of thereceiving-side SSD calculates the ratio of the amount of write data fromthe host 2, which is to be written to a write target block, to theamount of data to be copied to a copy destination block for a GCoperation (step S71), and performs the GC operation with the calculatedratio (step S72).

For example, when the receiving-side SSD is operating with a writeperformance of 1 Gbyte/s, and the write performance of the sending-sideSSD has been reduced to 512 Mbytes/s, the controller 4 of thereceiving-side SSD may reduce the write performance of thereceiving-side SSD to 512 Mbytes/s, and may use the remaining writeperformance (in this case, 512 Mbytes/s) for a GC operation. At thistime, the ratio of the amount of write data to the amount of data copiedfor the GC operation is 1 to 1. In step S72, a write operation and a GCoperation are performed in parallel so that the ratio of the amount ofwrite data from the host 2 to the amount of data copied for the GCoperation will become 1 to 1.

The flowchart of FIG. 21 shows the procedure of a throttling operationperformed by the receiving-side SSD when a notification of performancereduction has been received.

Based on the notified value related to the amount of reduction in thewrite performance of the sending-side SSD, the controller 4 of thereceiving-side SSD determines the number of NAND memory chips to besimultaneously driven in the receiving-side SSD, or a duty ratio forintermittently operating the NAND memory chips in the receiving-side SSD(step S81), and executes a write operation while performing a throttlingoperation based on the determined number of NAND memory chips or thedetermined duty ratio (step S82).

FIG. 22 shows a configuration example of an SSD that has both functionscorresponding to the sending-side SSD and the receiving-side SSD.

The controller 4 of the SSD 3 having both functions corresponding to thesending-side SSD and the receiving-side SSD includes the above-mentionedwrite performance reduction notification unit 24 and write performanceadjustment unit 25.

FIG. 23 shows a hardware configuration example of the informationprocessing apparatus that functions as the host 2.

The information processing apparatus is realized as a server computer ora personal computer.

The information processing apparatus may comprise a processor (CPU) 101,a main memory 102, a BIOS-ROM 103, a network controller 105, aperipheral interface controller 106, a controller 107, an embeddedcontroller (EC) 108, etc.

The processor 101 is a CPU configured to control the operation of eachcomponent of the information processing apparatus. The processor 101executes various programs loaded from any one of the SSDs 3 or fromanother memory device to the main memory 102. The main memory 102comprises a random access memory such as a DRAM. The programs executedby the processor 101 include the above-described application softwarelayer 41, the operating system 42, the file system 43 and the deviceperformance manager 44.

The network controller 105 is a communication device, such as a wiredLAN controller or a wireless LAN controller. The peripheral interfacecontroller 106 is configured to communicate with a peripheral device,such as a USB device.

The controller 107 is connected to a plurality of connectors 107A, andis configured to communicate with devices connected to the connectors107A. In the embodiment, plural SSDs 3 are connected to the respectiveconnectors 107A. The controller 107 may be a chip set having thefunction of a RAID controller. If the processor 101 includes a PCIeSwitch, each of the SSDs may be directly connected to the processor 101via a PCIe bus.

The EC 108 functions as a system controller configured to perform powermanagement of the information processing apparatus. The EC 108 turns onand off the information processing apparatus in response to a user'soperation of a power switch. The EC 108 is realized as a processingcircuit such as a one-chip microcontroller. The EC 108 may contain akeyboard controller for controlling an input device such as a keyboard(KB).

FIG. 24 shows a configuration example of the information processingapparatus including plural SSDs 3 and the host 2.

The information processing apparatus may comprise a thin box-shapedhousing 201 that can be accommodated in a rack. The SSDs 3 may bearranged in the housing 201. In this case, the SSDs 3 may be detachablyinserted in respective slots formed in the front surface 201A of thehousing 201.

A system board (mother board) 202 may be placed in the housing 201. Onthe system board (mother board) 202, various electronic components,which include the CPU 101, the memory 102, the network controller 105and the controller 107, are mounted. These electronic componentscooperate to function as the host 2.

As described above, the receiving-side SSD of the embodiment receives,from the host or another SSD, a notification indicative of a valuerelated to an amount of reduction in the write performance of saidanother SSD, and executes control for reducing its write performancebased on the value designated by the notification. Thus, thereceiving-side SSD can cooperate with the sending-side SSD havingreduced in write performance, which enables effective use of a period inwhich the write performance of the sending-side SSD is reduced.

The receiving-side SSD may have both functions of the sending-side SSDand the receiving-side SSD.

In addition, the embodiment employs a NAND memory as an example of thenonvolatile memory. However, the function of the embodiment is alsoapplicable to other various nonvolatile memories, such as amagnetoresistive random access memory (MRAM), a phase-change randomaccess memory (PRAM), a resistive random access memory (ReRAM), and aferroelectric random access memory (FeRAM).

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A memory system configured to operate as a firstsemiconductor storage device of a storage array in which data isdistributed across a plurality of semiconductor storage devicesincluding the first semiconductor storage device and a secondsemiconductor storage device, the memory system comprising: anonvolatile memory; and a controller electrically connected to thenonvolatile memory and configured to execute a write operation forwriting data, received from a host, to the nonvolatile memory, whereinthe controller is configured to: receive, from the host or the secondsemiconductor storage device of the storage array, a notificationindicating a value for a reduction in data-writing throughput of thesecond semiconductor device, wherein in a case where the data-writingthroughput of the second semiconductor device is reduced from a firstvalue to a second value, the notification indicates the second value ora value obtained by subtracting the second value from the first value;and vary data-writing throughput of the memory system based on thereceived notification so as to correspond to the value for the reductionin data-writing throughput of the second semiconductor device, whereinin a case where the data-writing throughput of the second semiconductordevice is reduced from the first value to the second value, thedata-writing throughput of the memory system is varied to the secondvalue based on the received notification.
 2. The memory system of claim1, wherein the controller is configured to: determine a ratio of anamount of data from the host to be written to the nonvolatile memory toan amount of data in the nonvolatile memory to be copied for a garbagecollection, based on the received notification; and execute the garbagecollection at the determined ratio.
 3. The memory system of claim 1,wherein the nonvolatile memory includes a plurality of nonvolatilememory chips; and the controller is configured to vary the number ofnonvolatile memory chips operated in parallel based on the receivednotification or vary an operating ratio based on the receivednotification.
 4. The memory system of claim 1, wherein the nonvolatilememory includes a plurality of nonvolatile memory chips; the receivednotification includes factor information indicating which one of a powerrestriction of the second semiconductor storage device, a garbagecollection of the second semiconductor storage device, and thermalprotection of the second semiconductor storage device is a cause for thereduction in data-writing throughput of the second semiconductor storagedevice; and the controller is configured to: execute a garbagecollection of the nonvolatile memory when the cause is the powerrestriction of the second semiconductor storage device or the garbagecollection of the second semiconductor storage device; and restrict thenumber of nonvolatile memory chips operated in parallel when the causeis the thermal protection of the second semiconductor storage device. 5.A memory system configured to operate as a first semiconductor storagedevice of a storage array in which data is distributed across aplurality of semiconductor storage devices including the firstsemiconductor storage device and a second semiconductor storage device,the memory system comprising: a nonvolatile memory; and a controllerelectrically connected to the nonvolatile memory and configured toexecute a write operation of writing data, received from a host, to thenonvolatile memory, wherein the controller is configured to: receive,from the host or the second semiconductor storage device of the storagearray, a notification providing a value indicating an amount ofreduction in data-writing throughput for write operation performance ofthe second semiconductor device and a cause of the reduction indata-writing throughput of the write operation performance in the secondsemiconductor storage device, wherein in a case where the data-writingthroughput of the second semiconductor device is reduced from a firstvalue to a second value, the notification indicates the second value ora value obtained by subtracting the second value from the first value;and vary performance of the write operation based on the value and thecause in the received notification so as to correspond to the value forthe reduction in data-writing throughput of the second semiconductordevice, wherein in a case where the data-writing throughput of thesecond semiconductor device is reduced from the first value to thesecond value, the data-writing throughput of the memory system is variedto the second value based on the value and the cause in the receivednotification.
 6. A control method for controlling a memory systemconfigured to operate as a first semiconductor storage device of astorage array in which data is distributed across a pluralitysemiconductor storage devices including the first semiconductor storagedevice and a second semiconductor storage device, the method comprising:executing a write operation for writing data, received from a host, to anonvolatile memory of a memory system, receiving, from the host or thesecond semiconductor storage device of the storage array, a notificationindicating a value for a reduction in data-writing throughput of thesecond semiconductor device, wherein in a case where the data-writingthroughput of the second semiconductor device is reduced from a firstvalue to a second value, the notification indicates the second value ora value obtained by subtracting the second value from the first value;and varying data-writing throughput of the memory system based on thereceived notification so as to correspond to the value for the reductionin data-writing throughput of the second semiconductor device, whereinin a case where the data-writing throughput of the second semiconductordevice is reduced from the first value to the second value, thedata-writing throughput of the memory system is varied to the secondvalue based on the received notification.
 7. The method of claim 6,wherein the varying the data-writing throughput of the memory systemincludes: determining a ratio of an amount of data from the host to bewritten to the nonvolatile memory to an amount of data in thenonvolatile memory to be copied for a garbage collection, based on thereceived notification; and executing the garbage collection at thedetermined ratio.
 8. The method of claim 6, wherein the nonvolatilememory includes a plurality of nonvolatile memory chips; and the varyingof the performance of the write operation includes restricting thenumber of nonvolatile memory chips operated in parallel.
 9. The methodof claim 6, wherein the nonvolatile memory includes a plurality ofnonvolatile memory chips; the received notification includes factorinformation indicating which one of a power restriction of the secondsemiconductor storage device, a garbage collection of the secondsemiconductor storage device, and thermal protection of the secondsemiconductor storage device is a cause of the reduction in the writeperformance of the second semiconductor storage device; and the varyingthe data-writing throughput of the memory system includes: executing thegarbage collection of the nonvolatile memory when the cause is the powerrestriction of the second semiconductor storage device or the garbagecollection operation of the second semiconductor storage device; andrestricting the number of nonvolatile memory chips operated in parallel,when the cause is the thermal protection of the second semiconductorstorage device.